1. Field of the Invention
The present invention relates to timers in computer systems, and more particularly, to implementation of high resolution, extended duration performance timers used for software development.
2. Description of the Related Art
As computer systems have evolved, applications for computers have also developed and expanded. Modern programs often include literally millions, even billions, of instructions and operations to be performed by the computer system. Although the high performance of modern computer systems allows these programs to be efficiently executed, the programmer must nonetheless carefully design these programs to achieve maximum efficiency and waste minimal time.
To assist software developers, some computer systems include performance timers in the computer system hardware to allow programmers to determine how long a particular operation requires for execution. For example, a programmer can measure the duration of a direct memory access transfer by reading the current value of the performance timer, executing the sequence and then reading the elapsed time. By measuring the time required for various operations and routines, the performance timer provides an invaluable tool to the programmer for evaluating system performance.
Because of the high speed of modern computers, the duration of most computer operations is quite short. Consequently, a performance timer must have sufficient resolution to accurately indicate the duration of an operation. On the other hand, to prevent the timer from rolling over to its initial value and complicating the time calculations, a performance timer preferably measures over an extended interval before it rolls over. Providing extended duration and adequate resolution, however, demands a performance timer generating a tremendous number of timer bits, which requires considerable hardware.
A new computer system incorporating the present invention has a data buffer which is coupled to several buses, and each bus includes numerous data bits. Limitations on the number of pins that may be provided on a single chip presented a significant design obstacle for interfacing all of the buses on a single buffer. Pin requirements thus forced the data buffer in the new computer system to be divided into multiple devices to provide sufficient pins for all of the bus bits. In a separate invention, on which an application is being concurrently filed, the data bits present in the new computer system are provided to the data buffer devices in an interleaved fashion of alternating pairs, bits 0 and 1 to one device, bits 2 and 3 to a second device, bits 4 and 5 to the first device, and so on. This allowed use of simpler memory error detection and correction techniques as compared to prior art systems. This invention is detailed in application Ser. No. 07/955,923, entitled ERROR CORRECTION SYSTEM FOR N BITS USING ERROR CORRECTION CODE DESIGNED FOR FEWER THAN N BITS, filed concurrently herewith and hereby incorporated by reference.
In the new computer system, as described in more detail below, the data buffer devices were the only devices receiving a large number of data bits on the buses. However, the alternating pair arrangement of the data bits in the data buffer devices ruled out the use of a conventional timer located in one of the data buffers or even a simple cascaded timer had each buffer been used to provide much wider sections, such as 16 or 32 bit portions of the data word. Another alternative was to use a dedicated device including the timer function and having connections to a sufficient number of the data bits. But this adds to the cost and complexity of the computer system and so is undesirable. Therefore a new timer arrangement was necessary to allow development of a performance timer having the desired resolution and duration without using additional devices.